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Checked by:
Category:
Language:
English
Total Size:
3.0 GB
Info Hash:
9CB8F080C5594D1A696EB2FE4646269C509ED2DE
Added By:
Added:
Oct. 23, 2023, 6:20 p.m.
Stats:
|
(Last updated: Sept. 5, 2025, 11:07 p.m.)
| File | Size |
|---|---|
| Get Bonus Downloads Here.url | 182 bytes |
| 1 - Interface Type English.vtt | 2.0 KB |
| 1 - Interface Type.mp4 | 11.3 MB |
| 2 - Course Framework English.vtt | 8.4 KB |
| 2 - Course Framework.mp4 | 47.7 MB |
| 54 - Agenda English.vtt | 775 bytes |
| 54 - Agenda.mp4 | 2.3 MB |
| 55 - Creating AXIS Master Interface P1 English.vtt | 22.4 KB |
| 55 - Creating AXIS Master Interface P1.mp4 | 145.3 MB |
| 56 - Creating AXIS Master Interface P2 English.vtt | 5.0 KB |
| 56 - Creating AXIS Master Interface P2.mp4 | 35.3 MB |
| 57 - Code.html | 1.3 KB |
| 58 - Agenda English.vtt | 613 bytes |
| 58 - Agenda.mp4 | 2.0 MB |
| 59 - Building AXIS Slave Interface with Verilog P1 English.vtt | 11.0 KB |
| 59 - Building AXIS Slave Interface with Verilog P1.mp4 | 37.1 MB |
| 60 - Building AXIS Slave Interface with Verilog P2 English.vtt | 13.2 KB |
| 60 - Building AXIS Slave Interface with Verilog P2.mp4 | 61.6 MB |
| 61 - Building AXIS Slave Interface with Verilog P3 English.vtt | 4.6 KB |
| 61 - Building AXIS Slave Interface with Verilog P3.mp4 | 23.3 MB |
| 62 - Code and BD.html | 2.1 KB |
| 63 - Agenda English.vtt | 917 bytes |
| 63 - Agenda.mp4 | 2.4 MB |
| 64 - Building AXIS Master Slave Interface with Verilog P1 English.vtt | 17.2 KB |
| 64 - Building AXIS Master Slave Interface with Verilog P1.mp4 | 57.5 MB |
| 65 - Building AXIS Master Slave Interface with Verilog P2 English.vtt | 7.2 KB |
| 65 - Building AXIS Master Slave Interface with Verilog P2.mp4 | 45.1 MB |
| 66 - Code and BD.html | 2.1 KB |
| 67 - Code and BD.html | 2.5 KB |
| 68 - Common Error 1 English.vtt | 2.8 KB |
| 68 - Common Error 1.mp4 | 19.1 MB |
| 69 - Common Error 2 English.vtt | 4.1 KB |
| 69 - Common Error 2.mp4 | 24.8 MB |
| 3 - Agenda English.vtt | 583 bytes |
| 3 - Agenda.mp4 | 2.3 MB |
| 4 - Slave Lite Interface without I O Ports P1 Creating IP English.vtt | 10.1 KB |
| 4 - Slave Lite Interface without I O Ports P1 Creating IP.mp4 | 55.3 MB |
| 5 - Slave Lite Interface without I O Ports P2 Creating IP English.vtt | 7.9 KB |
| 5 - Slave Lite Interface without I O Ports P2 Creating IP.mp4 | 49.3 MB |
| 6 - Slave Lite Interface without I O Ports P3 Creating IP English.vtt | 5.8 KB |
| 6 - Slave Lite Interface without I O Ports P3 Creating IP.mp4 | 39.2 MB |
| 7 - Slave Lite Interface without I O Ports P4 Creating C Application English.vtt | 11.3 KB |
| 7 - Slave Lite Interface without I O Ports P4 Creating C Application.mp4 | 76.3 MB |
| 8 - Slave Lite Interface without I O Ports P5 Creating C Application English.vtt | 4.8 KB |
| 8 - Slave Lite Interface without I O Ports P5 Creating C Application.mp4 | 38.4 MB |
| 9 - C Code.html | 791 bytes |
| 10 - Agenda English.vtt | 746 bytes |
| 10 - Agenda.mp4 | 2.6 MB |
| 11 - Adding Output port to Slave Lite Interface P1 English.vtt | 8.1 KB |
| 11 - Adding Output port to Slave Lite Interface P1.mp4 | 50.3 MB |
| 12 - Adding Output port to Slave Lite Interface P2 English.vtt | 5.0 KB |
| 12 - Adding Output port to Slave Lite Interface P2.mp4 | 37.1 MB |
| 13 - Adding Output port to Slave Lite Interface P3 English.vtt | 4.2 KB |
| 13 - Adding Output port to Slave Lite Interface P3.mp4 | 33.6 MB |
| 14 - Adding Input and Output ports to Slave Lite Interface P1 English.vtt | 7.5 KB |
| 14 - Adding Input and Output ports to Slave Lite Interface P1.mp4 | 44.8 MB |
| 15 - Adding Input and Output ports to Slave Lite Interface P2 English.vtt | 5.6 KB |
| 15 - Adding Input and Output ports to Slave Lite Interface P2.mp4 | 49.3 MB |
| 16 - Adding Input and Output ports to Slave Lite Interface P3 English.vtt | 2.7 KB |
| 16 - Adding Input and Output ports to Slave Lite Interface P3.mp4 | 23.0 MB |
| 17 - Agenda English.vtt | 964 bytes |
| 17 - Agenda.mp4 | 2.3 MB |
| 18 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P1 English.vtt | 8.5 KB |
| 18 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P1.mp4 | 24.5 MB |
| 19 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P2 English.vtt | 6.6 KB |
| 19 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P2.mp4 | 24.0 MB |
| 20 - Understanding Mandatory Signal Master read from Slave (Reading Ops) English.vtt | 3.9 KB |
| 20 - Understanding Mandatory Signal Master read from Slave (Reading Ops).mp4 | 12.0 MB |
| 21 - Other Signals in Slave Lite Interface English.vtt | 12.0 KB |
| 21 - Other Signals in Slave Lite Interface.mp4 | 89.6 MB |
| 22 - Block Design used in Demonstration English.vtt | 5.1 KB |
| 22 - Block Design used in Demonstration.mp4 | 38.0 MB |
| 23 - Analyzing Signals on ILA Probe English.vtt | 15.4 KB |
| 23 - Analyzing Signals on ILA Probe.mp4 | 98.2 MB |
| 24 - Agenda English.vtt | 1.5 KB |
| 24 - Agenda.mp4 | 5.0 MB |
| 25 - Add Existing RTL Delay Generator P1 English.vtt | 15.7 KB |
| 25 - Add Existing RTL Delay Generator P1.mp4 | 93.7 MB |
| 26 - Add Existing RTL Delay Generator P2 English.vtt | 5.9 KB |
| 26 - Add Existing RTL Delay Generator P2.mp4 | 43.8 MB |
| 27 - Adding Existing RTL Multiplier P1 English.vtt | 12.6 KB |
| 27 - Adding Existing RTL Multiplier P1.mp4 | 83.1 MB |
| 28 - Adding Existing RTL Multiplier P2 English.vtt | 4.6 KB |
| 28 - Adding Existing RTL Multiplier P2.mp4 | 43.3 MB |
| 29 - Adding Exisitng RTL COMPLEX FSM P1 English.vtt | 10.0 KB |
| 29 - Adding Exisitng RTL COMPLEX FSM P1.mp4 | 54.7 MB |
| 30 - Agenda English.vtt | 899 bytes |
| 30 - Agenda.mp4 | 1.9 MB |
| 31 - Fundamentals of Interrupt C Application English.vtt | 14.5 KB |
| 31 - Fundamentals of Interrupt C Application.mp4 | 80.6 MB |
| 32 - Adding Interrupt with RTL P1 English.vtt | 13.7 KB |
| 32 - Adding Interrupt with RTL P1.mp4 | 90.4 MB |
| 33 - Adding Interrupt with RTL P2 English.vtt | 17.6 KB |
| 33 - Adding Interrupt with RTL P2.mp4 | 149.2 MB |
| 34 - Code.html | 2.1 KB |
| 35 - Agenda English.vtt | 945 bytes |
| 35 - Agenda.mp4 | 2.1 MB |
| 36 - Using Vivado Interrupt Template Code P1 English.vtt | 17.9 KB |
| 36 - Using Vivado Interrupt Template Code P1.mp4 | 100.1 MB |
| 37 - Using Vivado Interrupt Template Code P2 English.vtt | 29.1 KB |
| 37 - Using Vivado Interrupt Template Code P2.mp4 | 213.6 MB |
| 38 - Code.html | 1.8 KB |
| 39 - Modifying Delay of the Vivado Interrupt Template English.vtt | 8.3 KB |
| 39 - Modifying Delay of the Vivado Interrupt Template.mp4 | 55.3 MB |
| 40 - Generating Continuous Interrupt P1 English.vtt | 6.1 KB |
| 40 - Generating Continuous Interrupt P1.mp4 | 41.5 MB |
| 41 - Generating Continuous Interrupt P2 English.vtt | 2.7 KB |
| 41 - Generating Continuous Interrupt P2.mp4 | 21.8 MB |
| 42 - Blinking Effect with Interrupt English.vtt | 18.7 KB |
| 42 - Blinking Effect with Interrupt.mp4 | 150.7 MB |
| 43 - Code.html | 2.3 KB |
| 44 - Agenda English.vtt | 792 bytes |
| 44 - Agenda.mp4 | 2.1 MB |
| 45 - Creating Master Interface with Vivado Template P1 English.vtt | 21.3 KB |
| 45 - Creating Master Interface with Vivado Template P1.mp4 | 162.5 MB |
| 46 - Creating Master Interface with Vivado Template P2 English.vtt | 7.6 KB |
| 46 - Creating Master Interface with Vivado Template P2.mp4 | 62.7 MB |
| 47 - Code.html | 576 bytes |
| 48 - Agenda English.vtt | 974 bytes |
| 48 - Agenda.mp4 | 2.6 MB |
| 49 - Building AXIS Slave Interface P1 English.vtt | 24.0 KB |
| 49 - Building AXIS Slave Interface P1.mp4 | 138.8 MB |
| 50 - Building AXIS Slave Interface P2 English.vtt | 7.6 KB |
| 50 - Building AXIS Slave Interface P2.mp4 | 65.5 MB |
| 51 - Code.html | 775 bytes |
| 52 - Building Complex FSM with existing FSM for AXIS English.vtt | 9.7 KB |
| 52 - Building Complex FSM with existing FSM for AXIS.mp4 | 64.0 MB |
| 53 - Code.html | 3.3 KB |
| Bonus Resources.txt | 386 bytes |
| Building Custom AXI Interface Peripherals for ZYNQ Devices.jpg | 10.8 KB |
| Building Custom AXI Interface Peripherals for ZYNQ Devices.txt | 6.5 KB |
Name
DL
Uploader
Size
S/L
Added
-
464.7 MB
[0
/
8]
2025-02-21
| Uploaded by freecoursewb | Size 464.7 MB | Health [ 0 /8 ] | Added 2025-02-21 |
-
922.3 MB
[3
/
0]
2023-12-14
| Uploaded by FreeCourseWeb | Size 922.3 MB | Health [ 3 /0 ] | Added 2023-12-14 |
-
903.3 MB
[4
/
0]
2023-11-30
| Uploaded by freecoursewb | Size 903.3 MB | Health [ 4 /0 ] | Added 2023-11-30 |
NOTE
SOURCE: Udemy Building Custom AXI Interface Peripherals for ZYNQ Devices
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