Torrent details for "Udemy VSD Physical Design Flow" Log in to bookmark
Controls:
×
Report Torrent
Please select a reason for reporting this torrent:
Your report will be reviewed by our moderation team.
×
Report Information
Loading report information...
This torrent has been reported 0 times.
Report Summary:
| User | Reason | Date |
|---|
Failed to load report information.
×
Success
Your report has been submitted successfully.
Checked by:
Category:
Language:
English
Total Size:
1.5 GB
Info Hash:
0BE6699C7D085C3EE818BCBC06B956D04DB9D433
Added By:
Added:
Oct. 23, 2023, 11:42 p.m.
Stats:
|
(Last updated: May 16, 2025, 6:40 a.m.)
| File | Size |
|---|---|
| Get Bonus Downloads Here.url | 180 bytes |
| 001 Floor-Planning Steps.mp4 | 11.9 MB |
| 001 Floor-Planning Steps_en.vtt | 14.9 KB |
| 002 Netlist Binding And Placement Optimization.mp4 | 15.2 MB |
| 002 Netlist Binding And Placement Optimization_en.vtt | 13.1 KB |
| 003 Placement Timing And Clock Tree Synthesis.mp4 | 18.3 MB |
| 003 Placement Timing And Clock Tree Synthesis_en.vtt | 12.7 KB |
| 004 Clock Net Shielding.mp4 | 14.7 MB |
| 004 Clock Net Shielding_en.vtt | 13.6 KB |
| 005 Route - DRC Clean - Parasitics Extraction - Final STA.mp4 | 22.2 MB |
| 005 Route - DRC Clean - Parasitics Extraction - Final STA_en.vtt | 12.7 KB |
| 001 Utilization Factor And Aspect Ratio.mp4 | 8.9 MB |
| 001 Utilization Factor And Aspect Ratio_en.vtt | 12.5 KB |
| 002 Concept Of Pre-Placed Cells.mp4 | 8.8 MB |
| 002 Concept Of Pre-Placed Cells_en.vtt | 13.3 KB |
| 003 De-coupling Capacitors.mp4 | 11.4 MB |
| 003 De-coupling Capacitors_en.vtt | 13.5 KB |
| 004 Power Planning.mp4 | 12.3 MB |
| 004 Power Planning_en.vtt | 15.0 KB |
| 005 Pin Placement And Logical Cell Placement Blockage.mp4 | 46.2 MB |
| 005 Pin Placement And Logical Cell Placement Blockage_en.vtt | 13.6 KB |
| 001 Net-list Binding And Placement.mp4 | 46.3 MB |
| 001 Net-list Binding And Placement_en.vtt | 13.2 KB |
| 002 Optimize Placement Using Estimated Wire Length And Capacitance.mp4 | 91.3 MB |
| 002 Optimize Placement Using Estimated Wire Length And Capacitance_en.vtt | 14.4 KB |
| 003 Optimize Placement Conitnued.mp4 | 86.9 MB |
| 003 Optimize Placement Conitnued_en.vtt | 12.1 KB |
| 001 Setup Timing Analysis And Introduction to Flip-Flop Setup Time.mp4 | 31.5 MB |
| 001 Setup Timing Analysis And Introduction to Flip-Flop Setup Time_en.vtt | 13.2 KB |
| 002 Introduction To Clock Jitter and Uncertainty.mp4 | 41.0 MB |
| 002 Introduction To Clock Jitter and Uncertainty_en.vtt | 10.6 KB |
| 003 Setup Timing Analysis with Multiple Clocks.mp4 | 34.4 MB |
| 003 Setup Timing Analysis with Multiple Clocks_en.vtt | 11.7 KB |
| 004 Multiple Clock Timing Analysis And Introduction To Data Slew Check.mp4 | 72.8 MB |
| 004 Multiple Clock Timing Analysis And Introduction To Data Slew Check_en.vtt | 12.5 KB |
| 005 Data Slew Check.mp4 | 82.8 MB |
| 005 Data Slew Check_en.vtt | 13.0 KB |
| 001 Clock Tree Routing And Buffering using H-Tree Algorithm.mp4 | 66.5 MB |
| 001 Clock Tree Routing And Buffering using H-Tree Algorithm_en.vtt | 12.9 KB |
| 002 Crosstalk And Clock Net Shielding.mp4 | 59.2 MB |
| 002 Crosstalk And Clock Net Shielding_en.vtt | 13.0 KB |
| 003 Static Timing Analysis With Real Clocks.mp4 | 47.7 MB |
| 003 Static Timing Analysis With Real Clocks_en.vtt | 15.9 KB |
| 004 Hold Timing Analysis Concluded.mp4 | 74.5 MB |
| 004 Hold Timing Analysis Concluded_en.vtt | 14.1 KB |
| 005 Multiple Clocks Setup Timing Analysis With Real Clocks.mp4 | 58.0 MB |
| 005 Multiple Clocks Setup Timing Analysis With Real Clocks_en.vtt | 11.4 KB |
| 001 Introduction to Maze Routing - Lee's Algorithm.mp4 | 88.2 MB |
| 001 Introduction to Maze Routing - Lee's Algorithm_en.vtt | 12.4 KB |
| 002 Lee's Algorithm Conclusion.mp4 | 114.9 MB |
| 002 Lee's Algorithm Conclusion_en.vtt | 14.0 KB |
| 003 Design Rule Check.mp4 | 99.5 MB |
| 003 Design Rule Check_en.vtt | 13.7 KB |
| 001 Introduction to IEEE 1481 - 1999 SPEF format.mp4 | 78.6 MB |
| 001 Introduction to IEEE 1481 - 1999 SPEF format_en.vtt | 12.5 KB |
| 002 SPEF Representation of a NET.mp4 | 65.8 MB |
| 002 SPEF Representation of a NET_en.vtt | 11.3 KB |
| 003 Distributed Resistance And Capacitance Representation in SPEF.mp4 | 79.0 MB |
| 003 Distributed Resistance And Capacitance Representation in SPEF_en.vtt | 14.2 KB |
| 004 SPEF Header Description, Physical Design Flow Conclusion and What Next !!.mp4 | 41.7 MB |
| 004 SPEF Header Description, Physical Design Flow Conclusion and What Next !!_en.vtt | 11.9 KB |
| Bonus Resources.txt | 386 bytes |
Name
DL
Uploader
Size
S/L
Added
-
406.1 MB
[0
/
1]
2023-10-23
| Uploaded by freecoursewb | Size 406.1 MB | Health [ 0 /1 ] | Added 2023-10-23 |
-
572.7 MB
[0
/
1]
2023-10-23
| Uploaded by freecoursewb | Size 572.7 MB | Health [ 0 /1 ] | Added 2023-10-23 |
-
591.1 MB
[0
/
7]
2023-10-23
| Uploaded by freecoursewb | Size 591.1 MB | Health [ 0 /7 ] | Added 2023-10-23 |
-
608.7 MB
[0
/
1]
2023-10-28
| Uploaded by freecoursewb | Size 608.7 MB | Health [ 0 /1 ] | Added 2023-10-28 |
-
2.0 GB
[36
/
38]
2023-10-26
| Uploaded by freecoursewb | Size 2.0 GB | Health [ 36 /38 ] | Added 2023-10-26 |
-
870.7 MB
[0
/
7]
2023-10-28
| Uploaded by freecoursewb | Size 870.7 MB | Health [ 0 /7 ] | Added 2023-10-28 |
-
1.0 GB
[28
/
30]
2023-10-26
| Uploaded by freecoursewb | Size 1.0 GB | Health [ 28 /30 ] | Added 2023-10-26 |
NOTE
SOURCE: Udemy VSD Physical Design Flow
-----------------------------------------------------------------------------------
COVER
-----------------------------------------------------------------------------------
MEDIAINFO
None
×