Torrent details for "Udemy RTL Finite State Machines in System Verilog" Log in to bookmark
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Checked by:
Category:
Language:
English
Total Size:
382.6 MB
Info Hash:
0E7A4D9B006F571D7958B8C81E98CAE6FDFC018D
Added By:
Added:
Oct. 24, 2024, 4:52 p.m.
Stats:
|
(Last updated: May 18, 2025, 3:47 a.m.)
| File | Size |
|---|---|
| Get Bonus Downloads Here.url | 182 bytes |
| 1 -Introduction.mp4 | 10.2 MB |
| 2 - How to use this course.html | 209 bytes |
| 2 -Learning Tips (Optional).mp4 | 5.4 MB |
| 3 -FSMs in Digital Logic.mp4 | 11.4 MB |
| 1 - Code Access.html | 340 bytes |
| 1 - Read This.html | 217 bytes |
| 1 -RTL FSM Design Pattern.mp4 | 8.7 MB |
| 1 -RTL GCD.mp4 | 5.5 MB |
| 2 -State Definitions.mp4 | 20.9 MB |
| 3 -Transition Arcs.mp4 | 16.8 MB |
| 4 -RTL Simulation - 1.mp4 | 19.2 MB |
| 5 -RTL Simulation - 2.mp4 | 23.6 MB |
| 6 -Synthesis.mp4 | 27.9 MB |
| 1 -Measure Latency - 1.mp4 | 31.3 MB |
| 2 -Measure Latency - 2.mp4 | 26.0 MB |
| 3 -Fewer States.mp4 | 32.4 MB |
| 4 -Synthesis.mp4 | 9.8 MB |
| 1 -One-Hot Encoding.mp4 | 8.6 MB |
| 2 -GCDOne Hot Encoded.mp4 | 25.5 MB |
| 3 -Simulation.mp4 | 4.9 MB |
| 4 -Synthesis.mp4 | 6.4 MB |
| 5 -Gatesim.mp4 | 13.0 MB |
| 1 -Wrap Up.mp4 | 13.4 MB |
| 1 - Recommended Setup Using Docker.html | 673 bytes |
| 1 -Docker Windows Install (Optional).mp4 | 14.0 MB |
| 2 - Download Docker Image.html | 256 bytes |
| 2 -Download Docker Image.mp4 | 7.1 MB |
| 3 - Run Docker with GUI (Windows).html | 822 bytes |
| 3 -Run Docker with GUI (Windows).mp4 | 6.7 MB |
| 4 - Run Docker with GUI (Linux - Ubuntu).html | 343 bytes |
| 4 - Run Docker with GUI (Mac OS).html | 765 bytes |
| 4 -Test Install.mp4 | 7.7 MB |
| 5 - Troubleshooting.html | 477 bytes |
| 1 - Simulation Only Setup.html | 279 bytes |
| 1 -EDA Playground Hints (Optional).mp4 | 26.3 MB |
| Bonus Resources.txt | 386 bytes |
Name
DL
Uploader
Size
S/L
Added
-
382.6 MB
[5
/
0]
2024-10-24
| Uploaded by freecoursewb | Size 382.6 MB | Health [ 5 /0 ] | Added 2024-10-24 |
-
802.0 MB
[2
/
8]
2026-03-21
| Uploaded by freecoursewb | Size 802.0 MB | Health [ 2 /8 ] | Added 2026-03-21 |
NOTE
SOURCE: Udemy RTL Finite State Machines in System Verilog
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COVER
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MEDIAINFO
None
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