Torrent details for "Udemy Learn FPGA design with VHDL Sobel Filter Edge Detection" Log in to bookmark
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Checked by:
Category:
Language:
English
Total Size:
1.7 GB
Info Hash:
B791847871CB77308C2E28092BCB6C1E57F0EDDE
Added By:
Added:
Sept. 26, 2025, 1:41 a.m.
Stats:
|
(Last updated: Sept. 26, 2025, 1:44 a.m.)
| File | Size |
|---|---|
| Get Bonus Downloads Here.url | 180 bytes |
| 1 -Introduction.mp4 | 78.9 MB |
| 1 -Digital image.mp4 | 77.0 MB |
| 2 -Gradient.mp4 | 71.0 MB |
| 3 -Convolution.mp4 | 44.3 MB |
| 4 -Sobel filter.mp4 | 40.4 MB |
| 5 -Edge detection steps.mp4 | 15.0 MB |
| 1 -Sign extension.mp4 | 19.9 MB |
| 2 -Binary addition - 1.mp4 | 83.5 MB |
| 3 -Binary addition - 2.mp4 | 9.5 MB |
| 4 -Binary shift.mp4 | 38.0 MB |
| 5 -Binary multiplication.mp4 | 38.3 MB |
| 6 -Binary division.mp4 | 12.2 MB |
| 1 -numeric_std package in VHDL.mp4 | 163.8 MB |
| 1 -State machine of the Sobel filter.mp4 | 39.5 MB |
| 2 -VHDL implementation - 1.mp4 | 108.9 MB |
| 3 -VHDL implementation - 2.mp4 | 64.0 MB |
| 4 -Simulation.mp4 | 83.5 MB |
| 1 -Architecture of the edge detection design.mp4 | 122.6 MB |
| 2 -The memories in the design.mp4 | 103.5 MB |
| 3 -VHDL implementation - 1.mp4 | 124.5 MB |
| 4 -VHDL implementation - 2.mp4 | 92.0 MB |
| 5 -Note about VGA.mp4 | 21.5 MB |
| 6 -Project folders organisation.mp4 | 16.9 MB |
| 7 -Automating with Makefile and python.mp4 | 122.2 MB |
| 8 -Demonstration.mp4 | 122.7 MB |
| Makefile | 5.0 KB |
| README | 104 bytes |
| image_1_160x120_grayscale1.png | 501 bytes |
| image_2_640x480_grayscale1.png | 1.7 KB |
| image_3_640x480_grayscale1.png | 6.4 KB |
| image_3_grayscale1.png | 5.9 KB |
| image_5_grayscale1.png | 36.3 KB |
| image_1_grayscale8.png | 2.8 KB |
| image_2_grayscale2.png | 15.5 KB |
| image_2_grayscale8.png | 142.3 KB |
| image_3_grayscale2.png | 5.0 KB |
| image_3_grayscale8.png | 8.8 KB |
| image_4_grayscale8.png | 2.3 MB |
| image_5_grayscale2.png | 2.3 KB |
| image_5_grayscale3.png | 49.1 KB |
| image_5_grayscale8.png | 2.8 MB |
| gen_vhdl_color_palette_rom.py | 3.2 KB |
| gen_vhdl_image_rom.py | 5.7 KB |
| gen_vhdl_pkg.py | 3.4 KB |
| memdump_to_img.py | 5.3 KB |
| color_palette_rom.vhd | 1.1 KB |
| edge_detection_pkg.vhd | 1.9 KB |
| image_ram.vhd | 1.7 KB |
| image_rom.vhd | 249.2 KB |
| sobel_filter.vhd | 2.7 KB |
| sobel_filter_parallel.vhd | 4.2 KB |
| tb_top.vhd | 1.3 KB |
| top.vhd | 9.8 KB |
| util_math_pkg.vhd | 606 bytes |
| vga_driver.vhd | 2.9 KB |
| constraints.ucf | 4.1 KB |
| 1 -Conclusion.mp4 | 3.2 MB |
| Bonus Resources.txt | 70 bytes |
Name
DL
Uploader
Size
S/L
Added
-
854.9 MB
[0
/
40]
2023-10-23
| Uploaded by freecoursewb | Size 854.9 MB | Health [ 0 /40 ] | Added 2023-10-23 |
-
343.8 MB
[13
/
0]
2025-04-03
| Uploaded by freecoursewb | Size 343.8 MB | Health [ 13 /0 ] | Added 2025-04-03 |
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834.1 MB
[13
/
7]
2025-03-07
| Uploaded by freecoursewb | Size 834.1 MB | Health [ 13 /7 ] | Added 2025-03-07 |
NOTE
SOURCE: Udemy Learn FPGA design with VHDL Sobel Filter Edge Detection
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COVER
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