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Total Size:
7.9 MB
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4080D32845491DC73BBC2C9A82D3068DB3B4958B
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July 4, 2025, 12:55 p.m.
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(Last updated: July 4, 2025, 12:55 p.m.)
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| ['Liu H. Circuit-Technology Co-Optimization of SRAM Design in Adv. CMOS Nodes 2024.pdf'] | 0 bytes |
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NOTE
SOURCE: Liu H. Circuit-Technology Co-Optimization of SRAM Design in Adv. CMOS Nodes 2024
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COVER
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MEDIAINFO
Textbook in PDF format Modern computing engines—CPUs, GPUs, and NPUs—require extensive SRAM for cache designs, driven by the increasing demand for higher density, performance, and energy efficiency. This book delves into two primary areas within ultra-scaled technology nodes: (1) advancing SRAM bitcell scaling and (2) exploring innovative subarray designs to enhance power-performance-area (PPA) metrics across technology nodes
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