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| File | Size |
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| Litovski V. Gm-C Filter Synthesis for Modern RF Systems 2022.pdf | 6.9 MB |
| Litovski V. Lecture Notes in Analog Electronics. Discrete and Integrated...2023.pdf | 9.2 MB |
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| Litovski V. Lecture Notes in Analog Electronics. Testing and Diagnosis...2025.pdf | 16.8 MB |
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NOTE
SOURCE: Litovski V. Lecture Notes in Analog Electronics. Testing and Diagnosis...2025
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COVER
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MEDIAINFO
Textbook in PDF format The process of designing, manufacturing, and maintenance of electronic circuits and systems inevitably includes their testing. It is not possible to deliver a quality and reliable industrial product to the market if it is not thoroughly tested. Hence, the ability to test one’s own product is in fact a requirement to market that product. Of course, as is well known, testing does not give the manufacturer new values but only the knowledge that the products he delivers to the market are good as expected. In some situations both the manufacturer and the maintenance support are facing the need to diagnose the failure which means to find the nature and the location of the fault causing malfunction of a circuit or system. That will be also solved based on testing. To bring the subject to the reader, in this book, we will visit several topics. When considering the concepts of testing, functional testing is the first idea that comes in mind. That means one is verifying the functionality of the designed system against the requirements given in advance by measurement. This and many other tests (such as temperature dependence) on the finished circuit or system are done most frequently. The problem is the number of test signals needed to activate the complete functionality of the system and related to this the time needed for testing a single product. Alternatively, one is to select a set of most probable faults and perform structural testing which means one will create test signals which will attack them (in general) only. To the structural testing is devoted the rest of the discussion since functional testing is self-defined. Most of our attention will be devoted to test signal synthesis for analog and for combinational digital circuits. This issue is almost entirely dependent on the circuit and system designer and is based on knowledge of both the functionality of the system and the failure modes in the life cycle of the product starting with design and ending with field exploitation. Procedures will be advised (and illustrated) leading to selection of test signals accommodated to the structure and the nature of the functionality of the system. In the heart of test signal synthesis is always the fault model which enables the verification of the synthesized signal and algorithm by simulation (which is an inevitable supportive tool to the test synthesizing engineer). Having in mind the almost unlimited number of possible faults in a circuit or system, effective fault simulation is a must for test synthesis both for analog and for mixed-signal circuits. Even small systems exhibit problems related to the accessibility to some points inside being needed for monitoring the response. Creating ports enabling accessibility has limited potential since it is bounded by the number of pins of the IC component or the pads of the printed circuit board. That is why the concept of design for testability (DFT) is most frequently adopted. It comprises a change in the structure of the system (mainly complex integrated circuits) which will enable access to many testing points (selected in advance) via a signal bus which is visiting parts of the system (under control of built-in hardware). System synthesis for testability is nowadays standardized which will be discussed below. A special problem arises in complex analog circuits to create an exciting signal which would activate a part of the whole while isolating the rest. That is solved by the concept of built-in test (BIT) or even the concept of built-in self-test (BIST). That comprises internal reconfiguration of the circuit so that its part being under test generates signals which are analyzed outside of the circuit (BIT) or even inside it (BIST). The issue of diagnosis is visited next. Here again, the structural view to the problem is considered which means that limited number of diagnostic hypotheses is created and memorized within the so-called fault dictionary. These hypotheses are, of course, related to the most probable faults and are generated by simulation. In that view the process of diagnosis represents a search through the fault dictionary (among the hypotheses) for the fault which produces a faulty response that is the most similar to the measured one. The problem is, of course, that in the context of analog circuits and when many faults are encompassed within the fault dictionary, there is a probability for some faulty responses to be similar. That is why here, among other methods, we strongly recommend the use of artificial neural networks (ANNs), being classifiers by nature, to help distinguish among them. To diagnose mixed-signal circuits a hierarchical procedure is advised and exemplified. That completes our proceedings related to testing and diagnosis. What follows is viewing the testing as an industrial activity. In that we will first analyze the nature of the faults. Then we will proceed with the analysis of the lifecycle of an electronic product marking the points where testing and diagnosis should be applied including the nature of them. Test equipment and economy of testing will be part of that analysis too. We are finishing with a chapter containing examples of test synthesis and diagnosis of some (mostly simple) circuits. Unlike other book of the LNAE series here there will be no chapter devoted to Spice simulation examples since Spice is extensively used throughout the previous chapters
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