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SOURCE: Ratschenberger J. From Code to Chip...Automated Analog Layout Design 2025
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COVER
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MEDIAINFO
Textbook in PDF format This book shows how the layout of an analog circuit can be automatically generated in a fully open-source way. Based on an exemplary design flow, it introduces and explains the necessary steps for transforming a SPICE netlist into a layout, which can be inspected by the open-source layout editor Magic VLSI. This is done by using the industry’s first open-source process design kit SKY130. Furthermore, the implementation of the design flow in the programming language Python is available as open-source on GitHub. By using the internal data structure, a reinforcement learning agent generates a placement by sequentially placing the devices in a layout. Hereby the agent learns a policy for solving the placement task of the given circuit, by doing multiples of these, which are rated by their estimated wire length and routing congestion. Besides this approach, there is also the ability to generate a placement by using a sequence-pair representation of it and simulated annealing optimization. After the placement is fixed, a two-stage routing algorithm connects the devices, as specified in the circuit. The first stage is a wire planner, which plans the routing on a rough tile-based grid and uses a negotiation-based algorithm to eliminate estimated routing congestions. The second stage is a detailed router that honors the planned guiding and lays out the actual resources in the routing space. Whereby for finding the routing tracks, a gridless approach is used that is based on the expansion of obstacles in the routing area and allows variable wire widths. In Chap. 1, the need of EDA tools for analog designs will be discussed, followed by a short introduction into the SKY130 PDK and the design methodology. Chapter 2 provides the theoretical basics of the most prominent algorithms used in this book. Chapter 3 covers the implementation of the internal data structures and algorithms, to capture a circuit from a SPICE netlist, to find known circuits in a larger one, and to generate and read in the cell views. In the subsequent Chap. 4, the capturing of the PDK and the handling of design rules will be discussed. The developed placement algorithms will be explained in Chap. 5, which also consists of a bottom-up approach for placing hierarchical circuits efficiently. Further, a legalization process will be discussed, for fixing non design rule compliant placements. In Chap. 6, the detailed routing space and the handling of obstacles will be introduced. That is followed by the description of the wire-planning and detailed routing algorithm. Chapter 7 presents the design results of a differential amplifier, a cross-coupled latch and a fully differential inverting amplifier. Whereby, for the placement of the differential amplifier, the learned policy of the reinforcement learning agent, was further studied. This chapter also includes a comparison of the implemented placement algorithms. Finally, Chap. 8 presents ideas for improvements of the design flow
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