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Total Size:
10.0 MB
Info Hash:
01E382934389D3466877E5F098D2D790AF9D9F0B
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Added:
April 21, 2026, 12:47 a.m.
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(Last updated: April 21, 2026, 12:51 a.m.)
| File | Size |
|---|---|
| Chang K. Functional Design Errors in Digital Circuits...2009.pdf | 10.0 MB |
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733.1 MB
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2024-12-18
| Uploaded by indexFroggy | Size 733.1 MB | Health [ 14 /3 ] | Added 2024-12-18 |
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14.6 MB
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2025-01-02
| Uploaded by indexFroggy | Size 14.6 MB | Health [ 14 /3 ] | Added 2025-01-02 |
NOTE
SOURCE: Chang K. Functional Design Errors in Digital Circuits...2009
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COVER
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MEDIAINFO
Textbook in PDF format Due to the dramatic increase in design complexity, modern circuits are often produced with functional errors. While improvements in verification allow engineers to find more errors, fixing these errors remains a manual and challenging task. Functional Design Errors in Digital Circuits Diagnosis covers a wide spectrum of innovative methods to automate the debugging process throughout the design flow: from Register-Transfer Level (RTL) all the way to the silicon die. In particular, this book describes: (1) techniques for bug trace minimization that simplify debugging; (2) an RTL error diagnosis method that identifies the root cause of errors directly; (3) a counterexample-guided error-repair framework to automatically fix errors in gate-level and RTL designs; (4) a symmetry-based rewiring technology for fixing electrical errors; (5) an incremental verification system for physical synthesis; and (6) an integrated framework for post-silicon debugging and layout repair. In addition, Functional Design Errors in Digital Circuits Diagnosis describes a comprehensive evaluation of spare-cell insertion methods. The solutions provided in this book can greatly reduce debugging effort, enhance design quality, and ultimately enable the design and manufacture of more reliable electronic devices
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