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Checked by:
Category:
Language:
English
Total Size:
2.8 GB
Info Hash:
4869B30ADB8EFC841777C861DD4E1C29EBB8BFBD
Added By:
Added:
Oct. 24, 2023, 4:05 a.m.
Stats:
|
(Last updated: May 22, 2025, 9:46 p.m.)
| File | Size |
|---|---|
| Get Bonus Downloads Here.url | 182 bytes |
| 001 Preview.mp4 | 84.6 MB |
| 001 Preview_en.vtt | 15.0 KB |
| 002 Sample program on edaplayground.mp4 | 87.8 MB |
| 002 Sample program on edaplayground_en.vtt | 13.1 KB |
| 001 Verilog fundamentals.mp4 | 165.6 MB |
| 001 Verilog fundamentals_en.vtt | 30.0 KB |
| 001 VLSI Design flow (FPGA & ASIC).mp4 | 76.5 MB |
| 001 VLSI Design flow (FPGA & ASIC)_en.vtt | 14.3 KB |
| 002 FPGA vs ASIC.mp4 | 80.1 MB |
| 002 FPGA vs ASIC_en.vtt | 8.7 KB |
| 001 Three levels of verilog design Description.mp4 | 32.9 MB |
| 001 Three levels of verilog design Description_en.vtt | 3.7 KB |
| 002 Example mux_2x1 with 3 abstracts models.mp4 | 9.1 MB |
| 002 Example mux_2x1 with 3 abstracts models_en.vtt | 1.8 KB |
| 001 Language constructs -Comments, keywords, identifier, Number specific, Operators.mp4 | 14.5 MB |
| 001 Language constructs -Comments, keywords, identifier, Number specific, Operators_en.vtt | 2.2 KB |
| 002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory.mp4 | 17.8 MB |
| 002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory_en.vtt | 3.0 KB |
| 003 Compiler Directives.mp4 | 15.9 MB |
| 003 Compiler Directives_en.vtt | 2.0 KB |
| 001 Verilog Program Structure -Module.mp4 | 7.4 MB |
| 001 Verilog Program Structure -Module_en.vtt | 1.1 KB |
| 002 Ports.mp4 | 10.7 MB |
| 002 Ports_en.vtt | 1.8 KB |
| 003 Port Connection Rules.mp4 | 13.0 MB |
| 003 Port Connection Rules_en.vtt | 1.9 KB |
| 004 Design Methodologies Approaches.mp4 | 4.7 MB |
| 004 Design Methodologies Approaches_en.vtt | 849 bytes |
| 001 Gate Level Model Introduction.mp4 | 3.4 MB |
| 001 Gate Level Model Introduction_en.vtt | 655 bytes |
| 002 Example 4x1 Mux.mp4 | 5.4 MB |
| 002 Example 4x1 Mux_en.vtt | 932 bytes |
| 003 Example Full Adder.mp4 | 3.6 MB |
| 003 Example Full Adder_en.vtt | 733 bytes |
| 004 Tri-state Buffers with Examples.mp4 | 12.9 MB |
| 004 Tri-state Buffers with Examples_en.vtt | 2.0 KB |
| 005 Array of Instance with example.mp4 | 10.7 MB |
| 005 Array of Instance with example_en.vtt | 1.6 KB |
| 001 Data flow Modeling assign statement.mp4 | 12.9 MB |
| 001 Data flow Modeling assign statement_en.vtt | 2.3 KB |
| 002 Operators.mp4 | 17.2 MB |
| 002 Operators_en.vtt | 1.9 KB |
| 003 Arithmetic Operators.mp4 | 8.5 MB |
| 003 Arithmetic Operators_en.vtt | 1.4 KB |
| 004 Logical Operators.mp4 | 12.7 MB |
| 004 Logical Operators_en.vtt | 1.6 KB |
| 005 Example Full Adder Logical operators.mp4 | 3.8 MB |
| 005 Example Full Adder Logical operators_en.vtt | 811 bytes |
| 006 Example Full Adder Arithmetic operators.mp4 | 2.8 MB |
| 006 Example Full Adder Arithmetic operators_en.vtt | 776 bytes |
| 007 Example Binary to Gray code converter.mp4 | 4.6 MB |
| 007 Example Binary to Gray code converter_en.vtt | 891 bytes |
| 008 Logical and , Logical or (&&, ).mp4 | 5.6 MB |
| 008 Logical and , Logical or (&&, )_en.vtt | 1.4 KB |
| 009 Shift operators Leftright Shift.mp4 | 17.9 MB |
| 009 Shift operators Leftright Shift_en.vtt | 2.3 KB |
| 010 Shifting without shift operator , just with concatenation operator.mp4 | 4.3 MB |
| 010 Shifting without shift operator , just with concatenation operator_en.vtt | 1.3 KB |
| 011 Ternary operator Example 2x1 MUX, 4x1 MUX.mp4 | 13.6 MB |
| 011 Ternary operator Example 2x1 MUX, 4x1 MUX_en.vtt | 3.2 KB |
| 012 Relational operators Example Comparator.mp4 | 4.5 MB |
| 012 Relational operators Example Comparator_en.vtt | 854 bytes |
| 013 Equality (==) , case Equality (===) operators.mp4 | 7.1 MB |
| 013 Equality (==) , case Equality (===) operators_en.vtt | 1.9 KB |
| 014 Reduction operator Example Parity Generator.mp4 | 7.1 MB |
| 014 Reduction operator Example Parity Generator_en.vtt | 1.3 KB |
| 38061230-arthm1.mp4 | 3.8 MB |
| 001 Behavioral Modeling - Introduction.mp4 | 67.0 MB |
| 001 Behavioral Modeling - Introduction_en.vtt | 7.8 KB |
| 002 Behavioral Modeling Constructs.mp4 | 15.4 MB |
| 002 Behavioral Modeling Constructs_en.vtt | 1.8 KB |
| 003 Procedural Blocks- initial & always.mp4 | 61.1 MB |
| 003 Procedural Blocks- initial & always_en.vtt | 7.6 KB |
| 004 Example Clock Generation.mp4 | 8.4 MB |
| 004 Example Clock Generation_en.vtt | 2.1 KB |
| 005 Assignment Statements - Blocking & Non-blocking.mp4 | 63.3 MB |
| 005 Assignment Statements - Blocking & Non-blocking_en.vtt | 7.0 KB |
| 006 Mechanism in Non-blocking.mp4 | 4.4 MB |
| 006 Mechanism in Non-blocking_en.vtt | 1.2 KB |
| 007 Concurrency.mp4 | 6.4 MB |
| 007 Concurrency_en.vtt | 1.2 KB |
| 008 Advantage of Non-blocking assignment Example swapping.mp4 | 10.2 MB |
| 008 Advantage of Non-blocking assignment Example swapping_en.vtt | 1.4 KB |
| 009 Advantage of Non-blocking assignment Example Pipelining.mp4 | 38.4 MB |
| 009 Advantage of Non-blocking assignment Example Pipelining_en.vtt | 5.6 KB |
| 010 if-else statement Example 4x1 Mux.mp4 | 30.4 MB |
| 010 if-else statement Example 4x1 Mux_en.vtt | 4.3 KB |
| 011 Case – statement Example 4x1 Mux.mp4 | 34.1 MB |
| 011 Case – statement Example 4x1 Mux_en.vtt | 3.6 KB |
| 012 Advantage of Case over if-else.mp4 | 8.0 MB |
| 012 Advantage of Case over if-else_en.vtt | 1.0 KB |
| 013 Loops while, for, repeat, forever.mp4 | 7.2 MB |
| 013 Loops while, for, repeat, forever_en.vtt | 1.4 KB |
| 014 Parallel blocks - fork-join.mp4 | 10.8 MB |
| 014 Parallel blocks - fork-join_en.vtt | 1.7 KB |
| 015 Combinational Logic Circuit Examples 8x1 Mux.mp4 | 7.6 MB |
| 015 Combinational Logic Circuit Examples 8x1 Mux_en.vtt | 1.8 KB |
| 016 Example 8x1 Mux using 4x1 mux and 2x1 mux.mp4 | 16.9 MB |
| 016 Example 8x1 Mux using 4x1 mux and 2x1 mux_en.vtt | 2.6 KB |
| 017 Example AND gate using 2x1 Mux.mp4 | 5.6 MB |
| 017 Example AND gate using 2x1 Mux_en.vtt | 2.1 KB |
| 018 Example 1x8 Demux.mp4 | 3.4 MB |
| 018 Example 1x8 Demux_en.vtt | 704 bytes |
| 019 Example Full Adder & 4-bit Full Adder.mp4 | 17.0 MB |
| 019 Example Full Adder & 4-bit Full Adder_en.vtt | 3.1 KB |
| 020 Example 3x8 Decoder and 3x8 Decoder using 2x4 decoder.mp4 | 10.3 MB |
| 020 Example 3x8 Decoder and 3x8 Decoder using 2x4 decoder_en.vtt | 2.0 KB |
| 021 Example 8x3 encoder.mp4 | 2.4 MB |
| 021 Example 8x3 encoder_en.vtt | 477 bytes |
| 022 Example Priority encoder.mp4 | 7.8 MB |
| 022 Example Priority encoder_en.vtt | 1.4 KB |
| 023 Example Seven Segment Display.mp4 | 13.4 MB |
| 023 Example Seven Segment Display_en.vtt | 1.9 KB |
| 024 Example ALU.mp4 | 5.4 MB |
| 024 Example ALU_en.vtt | 863 bytes |
| 025 Sequential Logic Circuits List of Examples.mp4 | 8.1 MB |
| 025 Sequential Logic Circuits List of Examples_en.vtt | 1.1 KB |
| 026 Example D Flip Flop vs D-Latch.mp4 | 17.1 MB |
| 026 Example D Flip Flop vs D-Latch_en.vtt | 2.1 KB |
| 027 Example Synchronous Reset D-Flip flop , Asynchronous Reset D-Flip flop.mp4 | 4.1 MB |
| 027 Example Synchronous Reset D-Flip flop , Asynchronous Reset D-Flip flop_en.vtt | 1.2 KB |
| 028 Example T-Flip Flop.mp4 | 8.1 MB |
| 028 Example T-Flip Flop_en.vtt | 2.2 KB |
| 029 Example Master-slave JK Flip Flop.mp4 | 6.1 MB |
| 029 Example Master-slave JK Flip Flop_en.vtt | 1.3 KB |
| 030 Example Counter.mp4 | 19.4 MB |
| 030 Example Counter_en.vtt | 3.7 KB |
| 031 Example UPDown Counter.mp4 | 27.4 MB |
| 031 Example UPDown Counter_en.vtt | 4.1 KB |
| 032 Example clock divider using counter- Divide by 2,4,8,.mp4 | 13.6 MB |
| 032 Example clock divider using counter- Divide by 2,4,8,_en.vtt | 1.7 KB |
| 033 Example Pulse Generator Mod-3 pulse generator.mp4 | 18.9 MB |
| 033 Example Pulse Generator Mod-3 pulse generator_en.vtt | 2.0 KB |
| 034 Example Divide by 3 clock.mp4 | 17.7 MB |
| 034 Example Divide by 3 clock_en.vtt | 2.4 KB |
| 035 Example Ring Counter vs Jonson Counter.mp4 | 11.8 MB |
| 035 Example Ring Counter vs Jonson Counter_en.vtt | 1.9 KB |
| 036 Example Shift Registers SISO, SIPO, PISO,PIPO.mp4 | 13.3 MB |
| 036 Example Shift Registers SISO, SIPO, PISO,PIPO_en.vtt | 1.7 KB |
| 037 Example LFSR (Linear Feedback Shift Register).mp4 | 35.1 MB |
| 037 Example LFSR (Linear Feedback Shift Register)_en.vtt | 5.1 KB |
| 038 memory design.mp4 | 27.0 MB |
| 038 memory design_en.vtt | 3.8 KB |
| 001 Switch level modeling.mp4 | 17.7 MB |
| 001 Switch level modeling_en.vtt | 3.2 KB |
| 001 Functional simulation.mp4 | 27.0 MB |
| 001 Functional simulation_en.vtt | 4.6 KB |
| 002 Example - Test bench for counter design.mp4 | 62.4 MB |
| 002 Example - Test bench for counter design_en.vtt | 5.4 KB |
| 003 Example - Test bench for Pulse generator.mp4 | 58.3 MB |
| 003 Example - Test bench for Pulse generator_en.vtt | 5.6 KB |
| external-assets-links.txt | 412 bytes |
| 001 Functions & tasks and system tasks.mp4 | 49.7 MB |
| 001 Functions & tasks and system tasks_en.vtt | 5.6 KB |
| 002 File based system tasks and random generator system task.mp4 | 68.5 MB |
| 002 File based system tasks and random generator system task_en.vtt | 7.4 KB |
| 003 Read file and write in to memory system task.mp4 | 18.9 MB |
| 003 Read file and write in to memory system task_en.vtt | 2.0 KB |
| 004 Programming Language Interface.mp4 | 13.5 MB |
| 004 Programming Language Interface_en.vtt | 1.3 KB |
| external-assets-links.txt | 633 bytes |
| 001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code.mp4 | 126.4 MB |
| 001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code_en.vtt | 22.6 KB |
| 002 Example FSM - Divide by 2 clock.mp4 | 11.5 MB |
| 002 Example FSM - Divide by 2 clock_en.vtt | 1.9 KB |
| 003 Example FSM- Divide by 3 clock.mp4 | 22.5 MB |
| 003 Example FSM- Divide by 3 clock_en.vtt | 2.6 KB |
| 001 Sequence detector using FSM with complete Design & TB.mp4 | 65.0 MB |
| 001 Sequence detector using FSM with complete Design & TB_en.vtt | 8.9 KB |
| 002 Sequence detector using FSM output waveform.mp4 | 13.3 MB |
| 002 Sequence detector using FSM output waveform_en.vtt | 1.2 KB |
| external-assets-links.txt | 212 bytes |
| 001 Memory controller with Design & TB.mp4 | 92.8 MB |
| 001 Memory controller with Design & TB_en.vtt | 10.0 KB |
| external-assets-links.txt | 212 bytes |
| 001 FIFO Lecture.mp4 | 1.1 MB |
| 001 FIFO Lecture_en.vtt | 60 bytes |
| 002 Introduction to FIFO.mp4 | 32.4 MB |
| 002 Introduction to FIFO_en.vtt | 4.4 KB |
| 003 Write Read Operation of Normal RAM.mp4 | 27.0 MB |
| 003 Write Read Operation of Normal RAM_en.vtt | 3.8 KB |
| 004 FIFO IO (input & Outputs).mp4 | 8.0 MB |
| 004 FIFO IO (input & Outputs)_en.vtt | 1.4 KB |
| 005 Block Diagram and Architecture of FIFO.mp4 | 44.5 MB |
| 005 Block Diagram and Architecture of FIFO_en.vtt | 4.2 KB |
| 006 Connection of FIFO design & Test bench environment.mp4 | 18.6 MB |
| 006 Connection of FIFO design & Test bench environment_en.vtt | 3.1 KB |
| 007 Verilog HDL for FIFO design.mp4 | 89.4 MB |
| 007 Verilog HDL for FIFO design_en.vtt | 12.4 KB |
| 008 Verilog HDL code for FIFO Test Bench.mp4 | 147.8 MB |
| 008 Verilog HDL code for FIFO Test Bench_en.vtt | 15.3 KB |
| 009 Run the simulation and finding errors and Analyze the waveform Results.mp4 | 61.2 MB |
| 009 Run the simulation and finding errors and Analyze the waveform Results_en.vtt | 6.8 KB |
| external-assets-links.txt | 78 bytes |
| 001 Hamming code complete Design & TB for error detection & correction.mp4 | 213.7 MB |
| 001 Hamming code complete Design & TB for error detection & correction_en.vtt | 19.5 KB |
| external-assets-links.txt | 689 bytes |
| 001 FPGA.mp4 | 131.7 MB |
| 001 FPGA_en.vtt | 14.9 KB |
| Bonus Resources.txt | 386 bytes |
Name
DL
Uploader
Size
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218.5 MB
[0
/
5]
2023-10-26
| Uploaded by freecoursewb | Size 218.5 MB | Health [ 0 /5 ] | Added 2023-10-26 |
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382.6 MB
[5
/
0]
2024-10-24
| Uploaded by freecoursewb | Size 382.6 MB | Health [ 5 /0 ] | Added 2024-10-24 |
-
735.3 MB
[2
/
1]
2023-10-23
| Uploaded by freecoursewb | Size 735.3 MB | Health [ 2 /1 ] | Added 2023-10-23 |
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SOURCE: Udemy Verilog HDL programming with practical approach
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